This invention relates to a logic circuit employing a two-terminal switching element having memory properties, and in particular a spin-valve element utilizing the tunneling magnetoresistance (TMR) effect or the giant magnetoresistance (GMR) effect.
Recent advances in nanoelectronics have been accompanied by the development of products which apply physical phenomena unique to minute-size magnetic materials, and there have been especially rapid advances in the field of spin electronics, in which the spin of free electrons in magnetic materials is utilized.
In this field of spin electronics, spin-valve elements which apply the tunneling magnetoresistance (TMR) effect occurring in a multilayer structure of a ferromagnetic layer, an insulating layer, and a ferromagnetic layer, or which apply the giant magnetoresistance (GMR) effect occurring in a multilayer structure of a ferromagnetic layer, a nonmagnetic layer (conducting layer), and a ferromagnetic layer, are currently regarded as having the highest possibility of practical application.
Such spin-valve elements are attracting the most attention for applications in magnetic random access memory (MRAM). This is because expectations are being placed on magnetic random access memory employing such spin-valve elements as a replacement for conventional DRAM (Dynamic Random Access Memory) and SDRAM (Synchronous DRAM).
These spin-valve elements are fundamentally bistable resistance elements, having two stable resistance values for a single applied voltage value. Hence if a logic circuit having memory properties is formed using such spin-valve elements, there is the possibility that the number of elements can be greatly reduced compared with logic circuits employing conventional silicon elements. Hence in light of efforts to raise integration levels and for other reasons, hopes are being placed on the realization of logic circuits employing these spin-valve elements.
However, at present there have been hardly any proposals of specific logic circuits which exploit the features of spin-valve elements. That is, in for example Patent Reference 1, formation of a programmable logic circuit using spin transistors is disclosed, but this circuit is based on conventional CMOS circuits, and does not necessarily take advantage of the high degree of integrability which is a feature of spin-valve elements.
Further, Patent Reference 2 proposes an element comprising a third electrode to detect its own potential in a magnetic layer of a spin-valve element, as well as a logic circuit using such an element; but a specific circuit configuration is not disclosed. Moreover, because the spin-valve element used as three terminals, the logic circuit does not have a structure suitable for high levels of integration.
Among logic circuits, there have in particular been no specific proposals regarding configurations in which flip-flop circuits (bistable circuits) which are necessary for sequential logic circuits are configured using spin-valve elements. Here, in sequential logic circuits, the output value is determined from the time series of input logic values up to that point in time.
Patent Reference 3 proposes a logic circuit (bistable circuit) configured using an organic bistable resistance element, having two stable resistance values for a single applied voltage value. An example of the logic circuit is shown in FIG. 9.
This logic circuit has a configuration in which a resistor element 103 is connected in series with a two-terminal switching element 101 which is an organic bistable resistance element, and operates as follows. That is, when the two-terminal switching element 101 is in a low-resistance state, by inputting a trigger pulse with prescribed voltage to the reset input terminal 107 in a state in which a DC bias voltage Vt is applied, the two-terminal switching element 101 transitions to a high-resistance state, and as a result the potential at the output terminal 109 changes from Vt-Von to Vt-Voff. Here Von is the terminal voltage of the element 101 in the low-resistance state, and Voff (>Von) is the terminal voltage of the element 101 in the high-resistance state.
On the other hand, when the two-terminal switching element 101 is in the high-resistance state, by inputting a trigger pulse with a prescribed voltage to the set input terminal 105 in a state in which a DC bias voltage Vt is applied, the two-terminal switching element 101 transitions to the low-resistance state, and as a result the potential at the output terminal 109 changes from Vt-Voff to Vt-Von. When trigger pulses are input simultaneously to the input terminals 105 and 107, the pulses cancel, and so there is no change in the state of the output terminal 109.
Hence this logic circuit functions as a so-called RS flip-flop.
Patent Reference 1: Japanese Patent Application Laid-open No. 2006-32915
Patent Reference 2: Japanese Patent Application Laid-open No. 2007-103663
Patent Reference 1: International Publication WO2006/22017
However, in the above logic circuit, the two-terminal switching element 101 comprising an organic bistable resistance element does not have memory properties, so that a bias voltage Vt must be applied continuously to maintain the state. Hence there are the drawbacks that current leaks to the bias voltage line when applying a write input pulse, and that there is wasteful power consumption.